-------------------------------------------------------------------------------
-- Title      : 
-- Project    : 
-------------------------------------------------------------------------------
-- File       : 
-- Author     : Allen Humphreys
-- Company    : 
-- Created    : 2010-09-29
-- Last update: 2010-09-29
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2010 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2010-09-29  1.0      Allen    Created
-------------------------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity dualcpu is
  port ( 
    CLK			    :		in	std_logic;  -- clock signal
    nReset		  :		in	std_logic;		-- reset for processor
    halt		    :		out	std_logic;		-- halt for processor
    ramAddr   : out std_logic_vector(15 downto 0);
    ramData   : out std_logic_vector(31 downto 0);
    ramWen    : out std_logic;
    ramRen    : out std_logic;
    ramQ      : in  std_logic_vector(31 downto 0);
    ramState  : in std_logic_vector(1 downto 0);
    memCtl    : in std_logic
  );
end dualcpu;

architecture struct of dualcpu is
  
  component coco is
    port ( 
      CLK			    :		in	std_logic;  -- clock signal
      nReset		  :		in	std_logic;		-- reset for processor
      
      adMemRead0      : in std_logic;                       -- dcache side
      adMemWrite0     : in std_logic;                       -- dcache side
      adMemWait0      : out  std_logic;                       -- dcache side
      adMemAddr0      : in std_logic_vector (15 downto 0);  -- dcache side
      adMemDataRead0  : out  std_logic_vector (31 downto 0);  -- dcache side
      adMemDataWrite0 : in std_logic_vector (31 downto 0);   -- dcache side
      
      adMemRead1      : in std_logic;                       -- dcache side
      adMemWrite1     : in std_logic;                       -- dcache side
      adMemWait1      : out  std_logic;                       -- dcache side
      adMemAddr1      : in std_logic_vector (15 downto 0);  -- dcache side
      adMemDataRead1  : out  std_logic_vector (31 downto 0);  -- dcache side
      adMemDataWrite1 : in std_logic_vector (31 downto 0);   -- dcache side
      
      
      cocoMemRead      : out std_logic;                       -- arbitrator side
      cocoMemWrite     : out std_logic;                       -- arbitrator side
      cocoMemWait      : in  std_logic;                       -- arbitrator side
      cocoMemAddr      : out std_logic_vector (15 downto 0);  -- arbitrator side
      cocoMemDataRead  : in  std_logic_vector (31 downto 0);  -- arbitrator side
      cocoMemDataWrite : out std_logic_vector (31 downto 0);   -- arbitrator side
      
      prMemRead0       :  in std_logic;
      prMemWrite0      :  in std_logic;
      prMemAddr0       :  in std_logic_vector(15 downto 0);
  
      prMemRead1       :  in std_logic;
      prMemWrite1      :  in std_logic;
      prMemAddr1       :  in std_logic_vector(15 downto 0);
      
      snoop_read0      :  out std_logic;
      snoop_write0     :  out std_logic;
      snoop_valid0     :  in  std_logic;
      extwrite0        :  in  std_logic;
      snoop_ReadData0  :  in  std_logic_vector(31 downto 0);
      
      snoop_read1      :  out std_logic;
      snoop_write1     :  out std_logic;
      snoop_valid1     :  in  std_logic;
      extwrite1        :  in  std_logic;
      snoop_ReadData1  :  in  std_logic_vector(31 downto 0)

    );
    
  
  end component;

component mycpu is
port ( 

  CLK							    :		in	std_logic;  -- clock signal
  nReset					     :		in	std_logic;  -- reset for processor
  halt						      :		out	std_logic;  -- halt for processor
  baseAddr        : in std_logic_vector(31 downto 0);
  
  dcMemRead        : out  std_logic;                       -- CPU side
  dcMemWrite       : out  std_logic;                       -- CPU side
  dMemWait        : in std_logic;                       -- CPU side
  dMemAddr        : out  std_logic_vector (15 downto 0);  -- CPU side
  dMemDataRead    : in std_logic_vector (31 downto 0);  -- CPU side
  dMemDataWrite   : out  std_logic_vector (31 downto 0);  -- CPU side
  
  iMemRead        : out  std_logic;                       -- CPU side
  iMemWait        : in std_logic;                       -- CPU side
  iMemAddr        : out  std_logic_vector (15 downto 0);  -- CPU side
  iMemData        : in std_logic_vector (31 downto 0);  -- CPU side
  ext_link        : out std_logic
);


end component;

component dcache is
  port(
    CLK            : in  std_logic;
    nReset         : in  std_logic;
    link           : in  std_logic;

    dMemRead       : in  std_logic;                       -- CPU side
    dMemWrite      : in  std_logic;                       -- CPU side
    dMemWait       : out std_logic;                       -- CPU side
    dMemAddr       : in  std_logic_vector (15 downto 0);  -- CPU side
    dMemDataRead   : out std_logic_vector (31 downto 0);  -- CPU side
    dMemDataWrite  : in  std_logic_vector (31 downto 0);  -- CPU side

    adMemRead      : out std_logic;                       -- arbitrator side
    adMemWrite     : out std_logic;                       -- arbitrator side
    adMemWait      : in  std_logic;                       -- arbitrator side
    adMemAddr      : out std_logic_vector (15 downto 0);  -- arbitrator side
    adMemDataRead  : in  std_logic_vector (31 downto 0);  -- arbitrator side
    adMemDataWrite : out std_logic_vector (31 downto 0);   -- arbitrator side
    adhalt         : in std_logic;
    cpuhalt        : out std_logic;

    snoop_read, snoop_write:        in  std_logic;				--external read / write control
    snoop_addr:                in  std_logic_vector(15 downto 0);	--external address
--snoop_link:                   in  std_logic;				--external link
    snoop_ReadData : out std_logic_vector(31 downto 0);

    snoop_valid:                 out std_logic;				--external valid flag
    extwrite:                 out std_logic				--external write flag
-- ext_link:                     out std_logic				--d-cache link flag
    );

end component;

component icache is
  port(
    CLK       : in  std_logic;
    nReset    : in  std_logic;

    iMemRead  : in  std_logic;                       -- CPU side
    iMemWait  : out std_logic;                       -- CPU side
    iMemAddr  : in  std_logic_vector (15 downto 0);  -- CPU side
    iMemData  : out std_logic_vector (31 downto 0);  -- CPU side

    aiMemWait : in  std_logic;                       -- arbitrator side
    aiMemRead : out std_logic;                       -- arbitrator side
    aiMemAddr : out std_logic_vector (15 downto 0);  -- arbitrator side
    aiMemData : in  std_logic_vector (31 downto 0)   -- arbitrator side
    );

end component;
  subtype address is std_logic_vector(15 downto 0);
  subtype word  is std_logic_vector(31 downto 0);
  subtype  bit is std_logic;


  signal	halt0, ramRen0, ramRen1	:	bit;



-------------------processor1 signals

  signal	halt1	:	std_logic;


--dcache0 signals
signal	dMemRead0, dMemWrite0, dMemWait0      : BIT;                       -- CPU side
signal  dMemAddr0, adMemAddr0       : ADDRESS;  -- CPU side
signal	adMemRead0, adMemWrite0, adMemWait0      : BIT;                       -- arbitrator side
signal  dMemDataRead0, dMemDataWrite0, adMemDataRead0, adMemDataWrite0       : WORD;  -- arbitrator side

--dcache1 signals
signal	dMemRead1, dMemWrite1, dMemWait1      : BIT;                       -- CPU side
signal  dMemAddr1, adMemAddr1       : ADDRESS;  -- CPU side
signal	adMemRead1, adMemWrite1, adMemWait1      : BIT;                       -- arbitrator side
signal   dMemDataRead1, dMemDataWrite1, adMemDataRead1, adMemDataWrite1       : WORD;  -- arbitrator side

--icache0 signals
signal  iMemRead0, iMemWait0  :  BIT;                       -- CPU side
signal	iMemAddr0, aiMemAddr0  :  ADDRESS;  -- CPU side
signal	aiMemWait0, aiMemRead0 :  BIT;                       -- arbitrator side
signal	iMemData0, aiMemData0 :  WORD;  -- arbitrator side

--icache1 signals
signal  iMemRead1, iMemWait1  :  BIT;                       -- CPU side
signal	iMemAddr1, aiMemAddr1  :  ADDRESS;  -- CPU side
signal	aiMemWait1, aiMemRead1 :  BIT;                       -- arbitrator side
signal	iMemData1, aiMemData1 :  WORD;  -- arbitrator side

signal ramready, cpuhalt0, cpuhalt1 : BIT;

signal poneholdsignal : BIT;
signal ramAddr0, ramAddr1 : ADDRESS;

signal link0, link1, d1_MemWait, d0_MemWait : BIT;

-----Coherency Signals
  signal chooseI0, chooseI1, chooseCOCO : BIT;
  
  
  signal cocoMemWait, cocoMemRead, cocoMemWrite, dcache1drain, dcache1drain0 : BIT;
  signal cocoMemAddr : ADDRESS;
  signal cocoMemDataWrite, snoop_ReadData0, snoop_ReadData1 : WORD;
  
  signal   snoop_read0, snoop_write0, snoop_valid0, extwrite0 : BIT;
  signal   snoop_read1, snoop_write1, snoop_valid1, extwrite1 : BIT;

begin
  
  
  COHERENCE : coco 
    port map( 
      CLK			    => CLK,		
      nReset		  => nReset,

      adMemRead0        => adMemRead0,--: in std_logic;                       -- dcache side
      adMemWrite0       => adMemWrite0,--: in std_logic;                       -- dcache side
      adMemWait0        => adMemWait0,--: out  std_logic;                       -- dcache side
      adMemAddr0        => adMemAddr0,--: in std_logic_vector (31 downto 0);  -- dcache side
      adMemDataRead0    => adMemDataRead0,--: out  std_logic_vector (31 downto 0);  -- dcache side
      adMemDataWrite0   => adMemDataWrite0,--: in std_logic_vector (31 downto 0);   -- dcache side
                        
      adMemRead1        => adMemRead1,--: in std_logic;                       -- dcache side
      adMemWrite1       => adMemWrite1,--: in std_logic;                       -- dcache side
      adMemWait1        => adMemWait1,--: out  std_logic;                       -- dcache side
      adMemAddr1        => adMemAddr1,--: in std_logic_vector (31 downto 0);  -- dcache side
      adMemDataRead1    => adMemDataRead1,--: out  std_logic_vector (31 downto 0);  -- dcache side
      adMemDataWrite1   => adMemDataWrite1,--: in std_logic_vector (31 downto 0);   -- dcache side
        
        
      cocoMemRead       => cocoMemRead, --: out std_logic;                       -- arbitrator side
      cocoMemWrite      => cocoMemWrite, --: out std_logic;                       -- arbitrator side
      cocoMemWait       => cocoMemWait, --: in  std_logic;                       -- arbitrator side
      cocoMemAddr       => cocoMemAddr, --: out std_logic_vector (15 downto 0);  -- arbitrator side
      cocoMemDataRead   => ramQ, --: in  std_logic_vector (31 downto 0);  -- arbitrator side
      cocoMemDataWrite  => cocoMemDataWrite, --: out std_logic_vector (31 downto 0)   -- arbitrator side
      
      prMemRead0       => dMemRead0,        --  in std_logic;
      prMemWrite0      => dMemWrite0,     --   in std_logic;
      prMemAddr0       => dMemAddr0, -- in std_logic_vector(15 downto 0);

      prMemRead1       => dMemRead1,  --in std_logic;
      prMemWrite1      => dMemWrite1, -- in std_logic;
      prMemAddr1       => dMemAddr1,  --in std_logic_vector(15 downto 0)
      
      snoop_read0      => snoop_read0,   --:  out std_logic;
      snoop_write0     => snoop_write0,  --  out std_logic;
      snoop_valid0     => snoop_valid0,  --:  in  std_logic;
      extwrite0        => extwrite0,     --:  in  std_logic;
      snoop_ReadData0  => snoop_ReadData0, --:  in  std_logic_vector(31 downto 0);
      
      snoop_read1      => snoop_read1,   --:  out std_logic;
      snoop_write1     => snoop_write1,  --:  out std_logic;
      snoop_valid1     => snoop_valid1,   --:  in  std_logic;
      extwrite1        => extwrite1,       --:  in  std_logic
      snoop_ReadData1  => snoop_ReadData1 --  in  std_logic_vector(31 downto 0);

      );
  


p0:	mycpu port map( 

  CLK		=>	CLK,
  nReset	=>	nReset,
  halt		=>	halt0,
  
  baseAddr => x"00000000",
  
  dcMemRead     =>   dMemRead0, 
  dcMemWrite    =>   dMemWrite0, 
  dMemWait      =>   dMemWait0,
  dMemAddr      =>   dMemAddr0,
  dMemDataRead  =>   dMemDataRead0, 
  dMemDataWrite =>   dMemDataWrite0,
  
  iMemRead      =>   iMemRead0,
  iMemWait      =>   iMemWait0, 
  iMemAddr      =>   iMemAddr0, 
  iMemData      =>   iMemData0,
  ext_link      =>   link0
  );

p1:	mycpu port map( 

  CLK		=>	CLK,
  nReset	=>	nReset,
  halt		=>	halt1,
  
  baseAddr => x"00000200",
  
  dcMemRead     =>   dMemRead1, 
  dcMemWrite    =>   dMemWrite1, 
  dMemWait      =>   dMemWait1,
  dMemAddr      =>   dMemAddr1,
  dMemDataRead  =>   dMemDataRead1, 
  dMemDataWrite =>   dMemDataWrite1,
  
  iMemRead      =>   iMemRead1,
  iMemWait      =>   iMemWait1, 
  iMemAddr      =>   iMemAddr1, 
  iMemData      =>   iMemData1,
  ext_link      =>   link1
  
  );



--- i-cache priority muxes
chooseI0 <= aiMemRead0;
chooseI1 <= (aiMemRead1 and not aiMemRead0);-- and aiMemRead);

--d-cache priority muxes
chooseCOCO <= cocoMemWrite or cocoMemRead;


ramAddr <= adMemAddr0 when dcache1drain0 = '1' else
           adMemAddr1 when dcache1drain = '1' else 
           cocoMemAddr when chooseCOCO = '1' else
           aiMemAddr0 when chooseCOCO = '0' and chooseI0 = '1' else
           aiMemAddr1 when chooseCOCO = '0' and chooseI0 = '0' and chooseI1 = '1' else
           x"AAAA";
           
           
           

cocoMemWait <= (not ramready and chooseCOCO) or ((chooseI1 or chooseI0) and not ramready);
aiMemWait0 <= (not ramready and chooseI0 and not chooseCOCO) or (chooseCOCO) or ((chooseI1) and not ramready);       
aiMemWait1 <= (not ramready and chooseI1 and not (chooseCOCO and chooseI0)) or chooseCOCO or chooseI0;

    ramWen <= adMemWrite0 when dcache1drain0 = '1' else
              adMemWrite1 when dcache1drain = '1' else cocoMemWrite;
    
  --ramWen <= '1' when (adMemWrite0 = '1' or (admemWrite1 = '1' and chooseD1 = '1')) else
            --'0';
                      
ramRen <=  '0' when dcache1drain = '1'  or dcache1drain0 = '1' else
           '1' when chooseCOCO = '1' and cocoMemRead = '1' else
           '1' when chooseCOCO = '0' and chooseI0 = '1' and aiMemRead0 = '1'else
           '1' when chooseCOCO = '0' and chooseI0 = '0' and chooseI1 = '1' and aiMemRead1 = '1' else
           '0';

  ramData <= adMemDataWrite0 when dcache1drain0 = '1' else
              adMemDataWrite1 when dcache1drain = '1' else cocoMemDataWrite;
                                
  --ramData <= adMemDataWrite0 when (chooseD0 = '1') else
    --         adMemDataWrite1 when (chooseD0 = '0' and chooseD1 = '1') else
       --      x"BBBBDDDD";

--poneholdsignal <= '0' when cpuhalt0 = '0' else nReset;

ramready <= '0' when ramstate = "01" or ramstate = "11" else
           '1';

--ramAddr0 <= aiMemAddr0(15 downto 0) when aiMemRead0 = '1' and adMemRead0 = '0' and adMemWrite0 = '0' else
         -- adMemAddr0(15 downto 0);

--ramAddr1 <= aiMemAddr1(15 downto 0) when aiMemRead1 = '1' and adMemRead1 = '0' and adMemWrite1 = '0' else
          --adMemAddr1(15 downto 0);  
          
--ramAddr <= ramAddr0 when cpuhalt0 = '0' else ramAddr1;  
          
--ramData <= adMemDataWrite0 when cpuhalt0 = '0' else adMemDataWrite1;
--ramRen
--ramWen

--aiMemWait0 <= (not ramready and aiMemRead0 and not adMemRead0 and not adMemWrite0) or ((adMemWrite0 or adMemRead0));-- and aiMemRead);
--adMemWait0 <= (not ramready and (adMemWrite0 or adMemRead0));

--aiMemWait1 <= (not ramready and aiMemRead1 and not adMemRead1 and not adMemWrite1) or ((adMemWrite1 or adMemRead1));-- and aiMemRead);
--adMemWait1 <= (not ramready and (adMemWrite1 or adMemRead1));


--ramWen <= '1' when (adMemWrite0 = '1' or adMemWrite1 = '1') else
   --       '0';

--ramRen  <= ramRen0 when cpuhalt0 = '0' else ramRen1;
          
--ramRen0 <= '1' when (aiMemRead0 = '1' or adMemRead0 = '1') and adMemWrite0 = '0'  and halt0 = '0' else
          --'0';
          
--ramRen1 <= '1' when (aiMemRead1 = '1' or adMemRead1 = '1') and adMemWrite1 = '0'  and halt1 = '0' else
          --'0';


--Instruction cache arbitration, both I caches wait if the coco is reading or writing
--   and I1 can only have access to ram when I0 isn't accessing it
 -- aiMemWait0 <=  (not ramready and aiMemRead0 and not cocoMemRead0 and not cocoMemWrite)
  --                 or ((cocoMemWrite or cocoMemRead0));
 -- aiMemWait1 <=  (not ramready and aiMemRead1 and not cocoMemRead0 and not cocoMemWrite and not aiMemRead0)
 --                or ((cocoMemWrite or cocoMemRead0));
                 
-- coco simply waits on ram, since it has top priority                 
 -- cocoMemWait <= (not ramready and (cocoMemWrite or cocoMemRead));


  --cocoMemWait <= (not ramready and (cocoMemRead or cocoMemWrite)) or --coco can access
               --   ((aiMemRead0 or aiMemRead1) and not ramready);      --coco must wait
  
  --aiMemWait0  <= (not ramready and aiMemRead0 and not cocoMemRead and not cocoMemWrite) or --exclusive access
                 --((aiMemRead1 or cocoMemRead or cocoMemWrite) and not ramready) or --wait on ai1 to finish
                 
                 --(aiMemRead0 and (cocoMemRead or cocoMemWrite));
                 
                 
  --aiMemWait1  <= (not ramready and aiMemRead1 and not aiMemRead0 and not cocoMemRead and not cocoMemWrite) or 
                -- ((aiMemRead0 or cocoMemRead or cocoMemWrite) and not ramready) or 
                 
                -- (aiMemRead1 and (aiMemRead0 or cocoMemRead or cocoMemWrite));--only assert wait if actually reading
  



-- RAM enable signals

  --ramWen <= '1' when (cocoMemWrite = '1') else
          --  '1' when (adMemWrite0 = '1' and dcache1drain0 = '1') or (adMemWrite1 = '1' and dcache1drain = '1') else
           -- '0';
                      
                      
 -- ramRen <= '1' when (aiMemRead0 = '1' or aiMemRead1 = '1' or cocoMemRead = '1') and cocoMemWrite = '0'
                 -- else  --these might not be correct
                 -- '0';  
                 
  --ramAddr <= aiMemAddr1 when aiMemRead1 = '1' and aiMemRead0 = '0' and cocoMemRead = '0' and cocoMemWrite = '0' else
           --  aiMemAddr0 when aiMemRead0 = '1' and cocoMemRead = '0' and cocoMemWrite = '0' else
           --  cocoMemAddr;
                              
  --ramData <= adMemDataWrite0 when (dcache1drain0 = '1' and dcache1drain = '0') else
         --    adMemDataWrite1 when (dcache1drain = '1') else
          --   cocoMemDataWrite ;
   
   with (dcache1drain0) select
        d0_MemWait <= not ramready and adMemWrite0 when '1',
                      adMemWait0 when others;         
dc0:	dcache port map(
    CLK   	=>	CLK,
    nReset      =>	nReset,
    link        => link0,

    dMemRead    =>	dMemRead0,
    dMemWrite   =>	dMemWrite0,
    dMemWait    =>	dMemWait0,
    dMemAddr    =>	dMemAddr0,
    dMemDataRead=>	dMemDataRead0,
    dMemDataWrite=>	dMemDataWrite0,

    adMemRead   =>	adMemRead0,
    adMemWrite  =>	adMemWrite0,
    adMemWait   =>	d0_MemWait,                       
    adMemAddr   =>	adMemAddr0,
    adMemDataRead   =>	adMemDataRead0,
    adMemDataWrite  =>	adMemDataWrite0,
    adhalt          => dcache1drain0,
    cpuhalt         => cpuhalt0,
    snoop_read     => snoop_read0, 
    snoop_write    => snoop_write0,--    in  std_logic;				--external read / write control
    snoop_addr     => adMemAddr1,         --  in  std_logic_vector(15 downto 0);	--external address
    --snoop_link:                   in  std_logic;				--external link
    snoop_ReadData => snoop_ReadData0,-- : out std_logic_vector(31 downto 0)
    
    snoop_valid   => snoop_valid0,     --             out std_logic;				--external valid flag
    extwrite      => extwrite0      --:                 out std_logic;				--external write flag
   -- ext_link:                     out std_logic				--d-cache link flag
    );
    

dcache1drain0 <= halt0 and halt1 and not cpuhalt0;

  dcache1drain <= cpuhalt0;
  with (dcache1drain) select
       d1_MemWait <= not ramready and adMemWrite1 when '1',
                     adMemWait1 when others;  
dc1:	dcache port map(
    CLK   	=>	CLK,
    nReset      =>	nReset,
    link        => link1,

    dMemRead    =>	dMemRead1,
    dMemWrite   =>	dMemWrite1,
    dMemWait    =>	dMemWait1,
    dMemAddr    =>	dMemAddr1,
    dMemDataRead=>	dMemDataRead1,
    dMemDataWrite=>	dMemDataWrite1,

    adMemRead   =>	adMemRead1,
    adMemWrite  =>	adMemWrite1,
    adMemWait   =>	d1_MemWait,                       
    adMemAddr   =>	adMemAddr1,
    adMemDataRead=>	adMemDataRead1,
    adMemDataWrite=>	adMemDataWrite1,
    adhalt          => dcache1drain,
    cpuhalt         => cpuhalt1,
    snoop_read     => snoop_read1, 
    snoop_write    => snoop_write1,--    in  std_logic;				--external read / write control
    snoop_addr     => adMemAddr0,         --  in  std_logic_vector(15 downto 0);	--external address
    --snoop_link:                   in  std_logic;				--external link
    snoop_ReadData => snoop_ReadData1, ---- : out std_logic_vector(31 downto 0)
    
    snoop_valid   => snoop_valid1,     --             out std_logic;				--external valid flag
    extwrite      => extwrite1      --:                 out std_logic;				--external write flag
   -- ext_link:                     out std_logic				--d-cache link flag
    );
    

ic0:	icache port map(
    CLK       =>	CLK,
    nReset    =>	nReset,

    iMemRead  =>	iMemRead0,
    iMemWait  =>	iMemWait0,
    iMemAddr  =>	iMemAddr0,
    iMemData  =>	iMemData0, --output > cpu

    aiMemWait =>	aiMemWait0,
    aiMemRead =>	aiMemRead0,
    aiMemAddr =>	aiMemAddr0,
    aiMemData =>	aiMemData0);

aiMemData0 <= ramQ;

ic1:	icache port map(
    CLK       =>	CLK,
    nReset    =>	nReset,

    iMemRead  =>	iMemRead1,
    iMemWait  =>	iMemWait1,
    iMemAddr  =>	iMemAddr1,
    iMemData  =>	iMemData1,

    aiMemWait =>	aiMemWait1,
    aiMemRead =>	aiMemRead1,
    aiMemAddr =>	aiMemAddr1,
    aiMemData =>	aiMemData1);

aiMemData1 <= ramQ;

halt <= cpuhalt0 and cpuhalt1;


end struct;
